例句與造句

1. At the logic synthesis stage , we make some research on the principles of logic synthesis at first , then by utilizing tsmc0 . 25um process , choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2 . 25v , and introducing the wireload library for effectively simulating delay and power consumption of wire connection , and taking the same clocks as in simulation , the critical path is 15 . 3ns and the chip area is 0 . 395mm2
   在進(jìn)行邏輯綜合時(shí)首先對邏輯綜合的原理作了一定的了解，然后利用tsmc的0 . 25 m的工藝庫，工作電壓為2 . 25v ，工作溫度最高可達(dá)到125攝氏度的最壞情況下，進(jìn)行邏輯綜合時(shí)引入了wireload庫以便有效的模擬連線所引起的延遲及功耗，采用與模擬時(shí)相同的時(shí)鐘，關(guān)鍵路徑為15 . 3ns ，芯片面積為0 . 395mm ~ 2 。
2. It's difficult to find synthesis stage in a sentence. 用synthesis stage造句挺難的